? semiconductor components industries, llc, 2014 september, 2014 ? rev. 1 1 publication order number: nvmfs5833n/d nvmfs5833n power mosfet 40 v, 7.5 m , 86 a, single n?channel, so?8fl features ? low r ds(on) ? low capacitance ? optimized gate charge ? aec?q101 qualified and ppap capable ? nvmfs5833nwf ? w ettable franks option for enhanced optical inspection ? these devices are pb?free and are rohs compliant maximum ratings (t j = 25 c unless otherwise noted) parameter symbol value unit drain?to?source v oltage v dss 40 v gate?to?source v oltage v gs 20 v continuous drain cur - rent r j?mb (notes 1, 2, 3 & 4) steady state t mb = 25 c i d 86 a t mb = 100 c 61 power dissipation r j?mb (notes 1, 2, 3 ) t mb = 25 c p d 112 w t mb = 100 c 56 continuous drain cur - rent r ja (notes 1, 3 & 4) steady state t a = 25 c i d 16 a t a = 100 c 11 power dissipation r ja (notes 1 & 3) t a = 25 c p d 3.7 w t a = 100 c 1.8 pulsed drain current t a = 25 c, t p = 10 s i dm 324 a operating junction and storage temperature t j , t stg ?55 to 175 c source current (body diode) i s 86 a single pulse drain?to?source avalanche energy (t j = 25 c, i l(pk) = 36 a, l = 0.1 mh) e as 65 mj lead temperature for soldering purposes (1/8 from case for 10 s) t l 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. thermal resistance maximum ratings parameter symbol value unit junction?to?mounting board (top) ? steady state (notes 2, 3) r j?mb 1.3 c/w junction?to?ambient ? steady state (note 3) r ja 41 1. the entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. psi ( ) is used as required per jesd51?12 for packages in which substantially less than 100% of the heat flows to single case surface. 3. surface?mounted on fr4 board using a 650 mm 2 , 2 oz. cu pad. 4. continuous dc current rating. maximum current for pulses as long as 1 second are higher but are dependent on pulse duration and duty cycle/ so?8 flat lead case 488aa style 1 marking diagram http://onsemi.com 5833 = specific device code xx = n (nvmfs5833n) or = wf (nvmfs5833nwf) a = assembly location y = year w = work week zz = lot traceability 5833xx aywzz 1 v (br)dss r ds(on) max i d max 40 v 7.5 m @ 10 v 86 a g (4) s (1,2,3) n?channel mosfet d (5) device package shipping ? ordering information nvmfs5833nt1g so?8fl (pb?free) 1500 / tape & ree l nvmfs5833nt3g so?8fl (pb?free) 5000 / tape & ree l ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specification s brochure, brd8011/d. s s s g d d d d NVMFS5833NWFT1G so?8fl (pb?free) 1500 / tape & ree l nvmfs5833nwft3g so?8fl (pb?free) 5000 / tape & ree l
nvmfs5833n http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise specified) parameter symbol test condition min typ max unit off characteristics drain?to?source breakdown voltage v (br)dss v gs = 0 v, i d = 250 a 40 v drain?to?source breakdown voltage temperature coefficient v (br)dss /t j 32.6 mv/ c zero gate voltage drain current i dss v gs = 0 v, v ds = 40 v t j = 25 c 1.0 a t j = 125 c 100 gate?to?source leakage current i gss v ds = 0 v, v gs = 20 v 100 na on characteristics (note 5) gate threshold voltage v gs(th) v gs = v ds , i d = 250 a 2.0 3.5 v threshold temperature coefficient v gs(th) /t j ?7.6 mv/ c drain?to?source on resistance r ds(on) v gs = 10 v, i d = 40 a 6.2 7.5 m forward transconductance g fs v ds = 5 v, i d = 5 a 38 s charges and capacitances input capacitance c iss v gs = 0 v, f = 1.0 mhz, v ds = 25 v 1714 pf output capacitance c oss 210 reverse transfer capacitance c rss 144 total gate charge q g(tot) v gs = 10 v, v ds = 32 v, i d = 40 a 32.5 nc threshold gate charge q g(th) 2.77 gate?to?source charge q gs 7.37 gate?to?drain charge q gd 9 switching characteristics (note 6) turn?on delay time t d(on) v gs = 10 v, v ds = 20 v, i d = 40 a, r g = 2.5 10.23 ns rise time t r 19.5 turn?off delay time t d(off) 23.60 fall time t f 3.00 drain?source diode characteristics forward diode voltage v sd v gs = 0 v, i s = 40 a t j = 25 c 0.85 1.2 v t j = 125 c 0.7 reverse recovery time t rr v gs = 0 v, d is /d t = 100 a/ s, i s = 40 a 23.5 ns charge time t a 13.5 discharge time t b 10 reverse recovery charge q rr 14 nc product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 5. pulse test: pulse width = 300 s, duty cycle 2%. 6. switching characteristics are independent of operating junction temperatures.
nvmfs5833n http://onsemi.com 3 typical characteristics 0 10 20 30 40 50 60 70 80 90 110 0 0.5 1.0 1.5 2.0 3.0 figure 1. on?region characteristics v ds , drain?to?source voltage (v) i d , drain current (a) 10 v v gs = 6 v 5.5 v 8 v 4.5 v 4.0 v 5.0 v t j = 25 c 0 10 20 30 40 50 60 70 80 12 3 4 7 v ds = 3 v t j = 25 c t j = ?55 c t j = 125 c figure 2. transfer characteristics v gs , gate?t o?source voltage (v) i d , drain current (a) 5 7 9 11 19 21 23 45 6 8 10 figure 3. on?resistance vs. gate?to?source voltage v gs , gate?t o?source voltage (v) r ds(on) , drain?to?source resistance (m ) i d = 40 a t j = 25 c 6.0 6.2 6.3 6.4 10 20 30 40 50 figure 4. on?resistance vs. drain current and gate voltage i d , drain current (a) r ds(on) , drain?to?source resistance (m ) t j = 25 c v gs = 10 v 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 ?50 ?25 0 25 50 75 100 125 150 175 figure 5. on?resistance variation with temperature t j , junction temperature ( c) r ds(on) , drain?to?source resistance (normalized) v gs = 10 v i d = 40 a 10 1000 10000 100000 20 25 30 figure 6. drain?to?source leakage current vs. voltage v ds , drain?to?source voltage (v) i dss , leakage (na) t j = 85 c t j = 150 c v gs = 0 v 100 2.5 56 90 100 110 79 17 15 13 6.1 15 10 5 100 t j = 125 c 5.9
nvmfs5833n http://onsemi.com 4 typical characteristics 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 01020 530 figure 7. capacitance variation v ds , drain?to?source voltage (v) c, capacitance (pf) t j = 25 c v gs = 0 v c iss c oss c rss 0 2 4 6 8 10 0 4 12 16 20 24 32 figure 8. gate?to?source v oltage vs. total charge q g , total gate charge (nc) v gs , gate?t o?source voltage (v) v gs = 10 v v dd = 32 v i d = 40 a t j = 25 c q t q gs q gd 1 10 100 1000 1 10 100 figure 9. resistive switching time variation vs. gate resistance r g , gate resistance ( ) t, time (ns) v dd = 20 v i d = 40 a v gs = 10 v t d(off) t d(on) t f t r 0 2 6 8 12 18 20 0.4 0.6 0.7 0.8 0.9 figure 10. diode forward voltage vs. current v sd , source?to?drain voltage (v) i s , source current (a) t j = 25 c v gs = 0 v 0.01 0.1 1 10 100 0.1 1 10 100 v gs = 10 v t c = 25 c 2 oz. 650 mm 2 cu pad r ds(on) limit thermal limit package limit 100 s 10 s 1 ms dc 10 ms figure 11. maximum rated forward biased safe operating area v ds , drain?to?source voltage (v) i d , drain current (a) 1 1e?06 1e?05 figure 12. avalanche characteristics time in avalanche (s) i peak (a) t j (initial) = 25 c 15 25 8 28 t j = 125 c 0.5 4 10 14 16 10 100 1e?04 1e?03 t j (initial) = 85 c
nvmfs5833n http://onsemi.com 5 typical characteristics 0.01 0.1 1 10 100 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 figure 13. thermal response pulse time (sec) r ja(t) ( c/w) effective transient thermal resistance 0.1 duty cycle = 0.5 0.2 0.05 0.02 0.01 single pulse
nvmfs5833n http://onsemi.com 6 package dimensions m 3.00 3.40 0 ??? 3.80 12 dfn5 5x6, 1.27p (so?8fl) case 488aa issue k notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeter. 3. dimension d1 and e1 do not include mold flash protrusions or gate burrs. 1234 top view side view bottom view d1 e1 d e 2 2 b a 0.20 c 0.20 c 2 x 2 x dim min nom millimeters a 0.90 1.00 a1 0.00 ??? b 0.33 0.41 c 0.23 0.28 d 5.15 d1 4.70 4.90 d2 3.80 4.00 e 6.15 e1 5.70 5.90 e2 3.45 3.65 e 1.27 bsc g 0.51 0.61 k 1.20 1.35 l 0.51 0.61 l1 0.125 ref a 0.10 c 0.10 c detail a 14 l1 e/2 8x d2 g e2 k b a 0.10 b c 0.05 c l detail a a1 e 3 x c 4 x c seating plane max 1.10 0.05 0.51 0.33 5.10 4.20 6.10 3.85 0.71 1.50 0.71 style 1: pin 1. source 2. source 3. source 4. gate 5. drain m *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 1.270 2x 0.750 1.000 0.905 0.475 4.530 1.530 4.560 0.495 3.200 1.330 0.965 2x 2x 3x 4x 4x pin 5 (exposed pad) 5.00 5.30 6.00 6.30 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 nvmfs5833n/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative
|
